1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device which requires refresh of data.
2. Description of the Background Art
FIG. 5 is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as a "DRAM") having a storage capacity of 16M bits.
Referring to FIG. 5, this DRAM includes control signal input terminals 30 to 32 and 34, an address signal input terminal group 33, a data signal input/output terminal group 35, a ground terminal 36, and a power supply terminal 37. This DRAM further includes a clock generating circuit 38, a row and column address buffer 39, an address switching circuit 40, an address generating circuit 41, a row decoder 42, a column decoder 43, a memory mat 44, an input buffer 47, and an output buffer 48. Memory mat 44 includes a memory array 45 and a sense refresh amplifier+input/output control circuit 46.
Clock generating circuit 38 selects a predetermined operation mode in response to signals ext./RAS and ext./CAS (in this specification and the drawings, /indicates that an activation level is at a logical low or L level) externally applied through control signal input terminals 30 and 31, and controls the whole DRAM.
Row and column address buffer 39 selectively provides address signals A0 to All externally applied through address signal input terminal group 33 to row decoder 42 and column decoder 43 during reading and writing operations. Address generating circuit 41 is activated in response to a refresh instruct signal/CBR output from clock generating circuit 38, and provides an address signal for refresh to row decoder 42 during a refresh operation. Address switching circuit 40 is controlled by the refresh instruct signal/CBR, connects row and column address buffer 39 and row decoder 42 during the reading and writing operations, and connects address generating circuit 41 and row decoder 42 during the refresh operation.
Memory array 45 has a storage capacity of 16M bits. Data of one bit is stored in one memory cell. Each memory cell is arranged at a predetermined address determined by a row address and a column address.
Row decoder 42 specifies a row address of memory array 45 in response to an address signal applied from row and column address buffer 39 or address generating circuit 41. Column decoder 43 specifies a column address of memory array 45 in response to an address signal applied from row and column address buffer 39.
Sense refresh amplifier+input/output control circuit 46 connects a memory cell at an address specified by row decoder 42 and column decoder 43 to one end of a global signal input/output line pair GIO during the reading and writing operations. Further, sense refresh amplifier+input/output control circuit 46 refreshes data of memory cells at the row address specified by row decoder 42 during the refresh operation.
The other end of global signal input/output line pair GIO is connected to input buffer 47 and output buffer 48. Input buffer 47 provides data input from data signal input/output terminal group 35 to a selected memory cell through global signal input/output line pair GIO in response to a signal ext./W externally applied through control signal input terminal 32 during the writing operation. Output buffer 48 outputs read data from the selected memory cell to data input/output terminal group 35 in response to a signal ext./OE input from control signal input terminal 34 during the reading operation.
FIG. 6 shows a chip layout of the DRAM shown in FIG. 5. Referring to FIG. 6, the DRAM includes four memory mats 44.1 to 44.4 each having a storage capacity of 4M bits. Memory mats 44.1 to 44.4 each include 16 memory arrays MA1 to MA16 each having a storage capacity of 256K bits. Four memory mats 44.1 to 44.4 constitute memory mat 44 of FIG. 5.
Row decoders 42.1 to 42.4 are arranged on respective chip center sides of memory mats 44.1 to 44.4 along chip longer sides. Row decoders 42.1 to 42.4 constitute row decoder 42 of FIG. 5.
Column decoders 43.1 to 43.4 are arranged on respective chip center sides of memory mats 44.1 to 44.4 along chip shorter sides. Column decoders 43.1 to 43.4 constitute column decoder 43 of FIG. 5. Clock generating circuit 38 shown in FIG. 5 and the like are arranged in a peripheral circuit region 49 at the chip center portion.
FIG. 7 is a circuit block diagram showing a configuration of memory array MA16 shown in FIG. 6 with one part omitted. Referring to FIG. 7, memory array MA16 includes a plurality of memory cells MC arranged in rows and columns, a word line WL provided corresponding to each memory cell row, and a bit line pair BLP provided corresponding to each memory cell column. Memory cell MC includes an MOS transistor Q for access and a capacitor C for information storage. Word line WL transmits output of row decoder 42.1 and activates memory cells MC of a selected row. Bit line pair BLP includes bit lines BL, /BL to which signals complementary to each other are transmitted, and carries out input and output of a data signal to and from selected memory cell MC.
A bit line equalize circuit 56 for equalizing bit lines BL, /BL to a bit line potential V.sub.BL (=Vcc/2) before selection of memory cell MC is arranged at one ends of bit lines BL, /BL. Bit line equalize circuit 56 includes N channel MOS transistors 53 and 54 connected between bit lines BL, /BL and a node N51, and an N channel MOS transistor 55 connected between bit lines BL and/BL. MOS transistors 53 to 55 receive a bit line equalize signal BLEQ at their gates. The bit line potential V.sub.BL (=Vcc/2) is applied to node N51. Node N51 is connected to bit line pair BLP of adjacent memory array MA15 through a transfer gate 52. Transfer gate 52 includes N channel MOS transistors 50 and 51. N channel MOS transistors 50 and 51 receive a signal BLI at their gates.
A sense refresh amplifier 61 for amplifying a small potential difference which appears between bit lines BL and /BL after selection of memory cell MC is arranged between bit lines BL and /BL. Sense refresh amplifier 61 includes N channel MOS transistors 57 and 58 connected between bit lines BL, /BL and a node N52, and P channel MOS transistors 59 and 60 connected between bit lines BL, /BL and a node N53. The gates of MOS transistors 57 and 59 are both connected to bit line /BL, and the gates of MOS transistors 58 and 60 are both connected to bit line BL. Nodes N52 and N53 receive sense amplifier activation signals /SE and SE output from a sense amplifier drive circuit 62, respectively. Sense amplifier drive circuit 62 is included in clock generating circuit 38 of FIG. 5.
The other ends of bit lines BL, /BL are connected to one ends of local signal input/output lines LIOL, /LIOL through a column select gate 65. Column select gate 65 includes N channel MOS transistors 63 and 64 connected between bit lines BL, /BL and local signal input/output lines LIOL, /LIOL, respectively. The gates of MOS transistors 63 and 64 are connected to column decoder 43.1 through a column select line CSL. The other end of local signal input/output line pair LIOL is connected to one end of global signal input/output line pair GIO of FIG. 5 through a block select switch, not shown. The other memory arrays MA1 to MA15 have the same configuration.
An operation of the DRAM shown in FIGS. 5 to 7 will be described briefly. In the writing operation, column decoder 43 pulls up column select line CSL of a column corresponding to an address signal to a logical high or H level which is an activation level to render column select gate 65 conductive. Further, the block select switch, not shown, is rendered conductive, and selected bit line pair BLP is connected to input buffer 47 through local signal input/output line pair LIO and global signal input/output line pair GIO.
Input buffer 47 applies write data from data signal input/output terminal group 35 to selected bit line pair BLP through global signal input/output line pair GIO and local signal input/output line pair LIO in response to the signal ext./W. The write data is applied as a potential difference between bit lines BL and /BL. Then, row decoder 42 pulls up word line WL of a row corresponding to the address signal to the H level which is an activation level, and renders MOS transistors Q of memory cells MC of the row. An amount of electric charge according to the potential of bit line BL or /BL is stored in capacitor C of selected memory cell MC.
Since electric charge of capacitor C of memory cell MC gradually flows out, refresh of data is carried out in a predetermined cycle. FIG. 8 is a timing chart showing the refresh operation. Upon detection that the signal ext./CAS falls before the signal ext./RAS falls, clock generating circuit 38 outputs the refresh instruct signal /CBR. In response to the falling of the signal ext./RAS, signals BLI and BLEQ fall, and MOS transistors 50 and 51 of transfer gate 52 and MOS transistors 53 to 55 of bit line equalize circuit 56 are disconnected.
In response to the signal /CBR, address generating circuit 41 outputs an address signal Add. which is different from the previously output address signal. Row decoder 42 pulls up word line WL of a row corresponding to the address signal Add. to the H level. The potentials of bit lines BL and /BL change only by a small amount according to the amount of electric charge of capacitor C of activated memory cell MC.
Then, sense amplifier drive circuit 62 pulls up the sense amplifier activation signal SE to the H level and pulls down the sense amplifier activation signal /SE to the L level to activate sense refresh amplifier 61. When the potential of bit line BL is higher than that of bit line /BL by a small amount, resistance values of MOS transistors 58 and 59 become smaller than those of MOS transistors 57 and 60, causing the potential of bit line BL to be pulled up to the H level and the potential of bit line /BL to be pulled down to the L level. On the contrary, when the potential of bit line /BL is higher than that of bit line BL by a small amount, resistance values of MOS transistors 57 and 60 become smaller than those of MOS transistors 58 and 59, causing the potential of bit line /BL to be pulled up to the H level and the potential of bit line BL to be pulled down to the L level.
When the signal ext./RAS rises to the H level which is a non-activation level, word line WL is pulled down to the L level which is a non-activation level. Refresh of data is thus completed.
In the reading operation, data of memory cells MC of a row selected by row decoder 42 is read out to bit line pair BLP as in the refresh operation, and data of bit line pair BLP of a column selected by column decoder 43 is provided to output buffer 48 through local signal input/output line pair LIO and global signal input/output line pair GIO. Output buffer 48 outputs read data to data signal input/output terminal group 35 in response to the signal ext./OE.
In such a DRAM, there is a variation in leakage current of memory cell MC among chips, leading to variation in cycle of data refresh. Therefore, a cycle of data refresh is measured for each chip, and respective chips are classified into a 32 ms product group and a 64 ms product group, for example, based on the measurement result. The 32 ms product refers to a chip which requires refresh of data every 32 ms per one memory cell MC, and the 64 ms product refers to a chip which requires refresh of data every 64 ms per one memory cell MC.
A DRAM chip is shipped as a 4K mode product or a 2K mode product depending on the user's need. A 4K mode refers to a mode in which only one word line WL is selected in one refresh operation. A 2K mode refers to a mode in which two word lines WL are selected in one refresh operation.
The DRAM shown in FIGS. 5 to 8 has approximately 4,000 word lines WL. Therefore, the 4K mode means that 4K refresh operations are required if word line WL is selected one by one. The 2K mode means that 2K refresh operations are required if word line WL is selected two by two.
Generally, the 32 ms product is set at the 2K mode, and shipped as a 2K mode 32 ms product. The 64 ms product is set at the 4K mode, and shipped as a 4K mode 64 ms product. A refresh cycle time required for one refresh operation is 32 ms/2K=16 .mu.s for the 2K mode 32 ms product, and 64 ms/4K=16 .mu.s for the 4K mode 64 ms product.
FIG. 9 is a circuit block diagram showing a configuration of a part related to the refresh operation of the DRAM shown in FIGS. 5 to 8. In the figure, a CBR signal generating circuit 38a outputs the refresh instruct signal/CBR in response to the signals ext./RAS and ext./CAS. CBR signal generating circuit 38a is included in clock generating circuit 38 of FIG. 5.
Address generating circuit 41 includes a pad 70, a refresh counter 71, and an address switching circuit 72. Pad 70 is bonded to a power supply line or a ground line, not shown, according to the 4K mode or the 2K mode. Refresh counter 71 counts the signal/CBR, and outputs the address signals A0 to A11 of 12 bits. The least significant bit of the output of counter 71 is the signal A0, and the most significant bit of the output of counter 71 is the signal All.
Address switching circuit 72 includes an address switching circuit 72a corresponding to the address signals A0 to A10, and an address switching circuit 72b corresponding to the address signal A11. Address switching circuit 72a directly passes the address signals A0 to A10. Address switching circuit 72b passes the address signal All when pad 70 is bonded to the power supply line and the 4K mode is selected, and prevents passing of the address signal All when pad 70 is bonded to the ground line and the 2K mode is selected.
Address switching circuit 40 includes an address switching circuit 40a corresponding to the address signals A0 to A10, and an address switching circuit 40b corresponding to the address signal A11. Address switching circuit 40 provides the address signals A0 to All from row and column address buffer 39 to row decoder 42 during the writing and reading operations, and provides the address signals A0 to A11 or the address signals A0 to A10 from address switching circuit 72 in response to the refresh instruct signal/CBR. Row decoder 42 selects one word line WL in memory array 45 in response to the address signals A0 to A11, and selects two word lines WL in memory array 45 in response to the address signals A0 to A10.
The signal A11 is for determining whether word line WL to be selected belongs to memory arrays MA1 to MA4 or memory arrays MA5 to MA8, as shown in FIG. 10. Therefore, in the 4K mode in which the signal A11 is provided, one memory array (for example, MA1) to which word line WL belongs is determined, and one word line WL belonging to memory array MA1 is selected. However, in the 2K mode in which the signal A11 is not provided, it is not determined which of two memory arrays (for example, MA1 and MA5) word line WL belongs to, and one word line WL belonging to memory array MA1 and one word line WL belonging to memory array MA5 are simultaneously selected.
However, in the conventional DRAM, when the user sets the refresh cycle time to a standard value of a long refresh product which is larger than a standard value (16 .mu.s) of an ordinary product in order to gain write and read times, data disappears if the ability of a chip as a long refresh product is marginal.
On the contrary, the user may set the refresh cycle time far shorter than the standard value (16 .mu.s) for fear of disappearance of data. In this case, current consumption is increased.